This invention relates generally to methods and circuits for converting conventional digital logic signals to high-speed, low-voltage differential signals.
The Telecommunications Industry Association (TIA) published a standard specifying the electrical characteristics of low-voltage differential signaling (LVDS) interface circuits that can be used to interchange binary signals. LVDS employs low-voltage differential signals to provide high-speed, low power data communication. The use of differential signals allows for cancellation of common-mode noise, and thus enables data transmission with exceptional noise immunity. For a detailed description of this LVDS standard, see xe2x80x9cElectrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits,xe2x80x9d TIA/EIA-644 (March 1996), which is incorporated herein by reference.
FIG. 1A (prior art) illustrates an LVDS generator G having differential output terminals A and B connected to opposite terminals of a 100 ohm load resistor RL. FIG. 1B (prior art) is a waveform diagram depicting the signaling sense of the voltages appearing across load resistor RL.
LVDS generator G produces a pair of differential output signals VA and VB. The LVDS standard requires that these signals be in the range of 250 mV to 450 mV across the 100 ohm load resistor RL, and that the voltage midway between the two differential voltages remains at approximately 1.2 volts. As depicted in FIGS. 1A and 1B, to represent a binary one, terminal A of generator G is negative with respect to terminal B, and to represent a binary zero, terminal A is positive with respect to terminal B.
Some conventional integrated circuits (ICs) are adapted to provide differential output signals that conform to the LVDS specification. However, ICs that provide two-level logic signals on single output pins are more common. In some systems there may be a need to communicate signals between a circuit that does not conform to the LVDS specification and a circuit that does conform. There is therefore a need for a means of converting single logic signals to LVDS and other types of differential logic signals.
The present invention addresses the need for a means of converting typical two-level logic signals to differential logic signals. In accordance with one embodiment, a field programmable gate array (FPGA) is configured to provide a digital signal and its complement on a pair of output pins. A resistor network connected to these output pins converts the complementary signals to a pair of differential input signals having current and voltage levels within the range established by the LVDS specification. For maximum efficiency, the values of the resistors that make up the resistor network can be selected to match the 100 ohm input resistance exhibited by LVDS receivers.
This summary does not limit the invention, which is instead defined by the appended claims.